Adaptive Computation of Higher Order Moments and its Systolic Realization

In signal processing applications that require new estimates of the fourth and lower order moments every time a new data sample is received, it is necessary to design algorithms that adaptively update these terms. In addition, if real-time performance is necessary we should transform these algorithms so that their parallel processing and pipelining potential is exploited by a suitable multiprocessor architecture. In this paper we present a timeand order-recursive estimation procedure for updating all moment lag estimates (up to the fourth order) in one of their primary region of support, using the previous estimates and the newly arrived data sample in real-time. Then we systematically transform the moments updating algorithm onto an architecture that is suitable for VLSI implementation. As a special case a linear array computing the diagonal 1-D slice of the higher order moments is also synthesized. Under the algorithm-to-architectures transformation the timeand orderrecursive characteristics of the adaptive procedure translate to a scalable architecture whose processing elements consist of pipelined stages of simple multiply-accumulate units. The uni ed top-down synthesis of the architectures facilitates formal veri cation of correctness at the behavioral level, identi cation of trade-o s, and the easy introduction of modi cations, should the design objectives change during the design phase.